• Power consumption of AI/xPU processors have climbed dramatically and are projected to continue doing so.

• Lower operating voltages cause current consumption to increase even faster than power consumption.

• Lateral power distribution leads to large conductive losses and voltage transients due to load current steps which only get worse with continued increase in power consumption.

(Lateral Power Delivery Network)

Vertical Power Delivery (VPD) brings voltage regulation closer to high-current processors by delivering power through the vertical dimension of the system, rather than routing high current laterally across the motherboard.By shortening the electrical path between the voltage regulator and the processor, VPD reduces power distribution network (PDN) resistance and inductance, enabling efficient, high-current power delivery for advanced AI, HPC and data-center processors.

Shorter Power Delivery Path: Conventional power architectures place voltage regulators beside the processor and distribute high current laterally through PCB copper, package connections and the processor substrate. Vertical Power Delivery positions the final stage of voltage conversion underneath, within or directly adjacent to the processor package, significantly reducing the distance between the regulator and the load.

Point-of-Load Voltage Conversion: Instead of transporting the processor's full load current over long board-level paths, power can be distributed at a higher voltage and converted closer to the processor. This reduces current in the upstream power path and moves high-current distribution closer to where power is consumed.

Package-Level Integration: Vertical Power Delivery can be implemented using voltage regulators attached to the back side of the PCB, positioned on the land side of the processor package, or integrated directly into the package substrate. The optimal architecture depends on processor power, package construction, thermal constraints and system requirements.

Lower PDN Losses: Shortening the high-current path reduces resistive losses and voltage drop between the voltage regulator and processor.

Lower Parasitic Inductance: Placing regulation closer to the load reduces interconnect inductance, improving the electrical behavior of the power delivery network during rapid changes in processor current.

Faster Transient Response: A shorter, lower-impedance PDN allows the voltage regulator to respond more effectively to fast load transients generated by modern processors and AI accelerators.

Higher Current Density: Vertical architectures reduce dependence on large lateral copper paths and allow power conversion to occupy areas underneath or within the processor package, enabling increasingly high-current systems within constrained board area.

Improved Board Utilization: Moving voltage regulation away from the perimeter of the processor frees valuable PCB area otherwise required for large voltage-regulator stages, inductors, capacitors and high-current routing.

Ferric Integrated Voltage Regulators are designed to place high-density voltage conversion as close as possible to the processor load. Ferric integrates the power switches, control circuitry, capacitors and thin-film magnetic inductors into extremely compact voltage regulators, enabling power conversion architectures that would be difficult to implement using conventional discrete voltage-regulator solutions.

As AI and high-performance processors move toward increasingly high current levels, conventional lateral power delivery becomes progressively more constrained by resistance, inductance, board area and power density. Ferric's high-current-density IVRs enable scalable vertical power delivery architectures by moving the final voltage-conversion stage closer to the processor and reducing the distance over which low-voltage, high-current power must travel.The result is a shorter, lower-impedance power delivery network designed for the current density and transient requirements of next-generation processors.